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    • 专利摘要:
    1. A DEVICE FOR ASSESSING THE IMAGE CONTOUR, comprising a serially connected receiving unit, a quantization and coding unit, an adder and a prediction unit, the output of which is connected to another input of the adder, in order to improve the quality of the image, the prediction unit consists of sequential memory device, a processing unit for horizontal and vertical elements of the image contour, an assessment unit for the angular position of the image contour, a coordinate discriminator, three memory blocks of the prediction evaluation unit, the signal detector and the selector, while the inputs of the horizontal and vertical image processing unit are connected to the outputs of the serial storage bits, the first information output is connected to the first information input of the forecast evaluation unit, the second information output and two control outputs - respectively to the first information input, the Reset input and the control input of the block for estimating the angular position of the image contour, the third and fourth information e outputs - to the information inputs of the coordinate discriminator, the other inputs of which are connected to the corresponding outputs of the image position angle estimation block, and the output - to the information input of the first memory block, the first output of which is connected to the second information input of the prediction evaluation block, the first control output C of the processing unit of the horizontal and vertical elements of the image contour is connected to the control inputs of the first and second memory blocks, the first information output d - Oi with the input of the third memory block, the outputs of the three memory blocks with other information inputs of the image position angle estimation block, the output of the second memory block with the second control input of the first memory block, other information inputs of the proxy estimation block - with additional outputs; rubbing. its bit of the serial memory, the output of the forecast evaluation unit - with the inputs of the selector and the signal detector, the output of which is connected to the control input of the selector, the other input of the KOTOW that is connected to the output of the first bit of the serial memory.
    公开号:SU1076002A3
    申请号:SU813255245
    申请日:1981-02-27
    公开日:1984-02-23
    发明作者:Ришар Кристиан；Бенвенист Альбер；Кретц Франси
    申请人:Л' Эта Франсэ Репрезанте Пар Ле Секретэр Дъэта О Пост Э Телекоммюникасьон Э А Ля Теледиффюзьон /Сантр Насьональ Д.Этюд Де Телекоммюникасьон (Фирма)；Этаблиссман Пюблик Де Диффюзьон Ди "Теледиффюзьон Де Франс" (Фирма)；
    IPC主号:
    专利说明:

    2, the device according to claim 1, characterized in that the processing unit of horizontal and vertical elements of the image contour consists of two calculators of the absolute value of the difference of the input signals, five comparison elements, two summing counters, two registers, AND and OR elements and an inverter, this is the first absolute value calculator, the first element of the comparison, the first summing counter and the first register are connected in series, the second calculator of the absolute value of the difference of the input signals, the second comparison element, the second summing counter and the second register are connected in series, the first input of the OR element is connected to the output of the first summing counter via the third comparison element, the second input to the output of the first comparison element through the inverter, the third input to the output of the second summing counter through the fourth element comparison, and the output - with the first input element And, the second input of which is connected to the output of the second summing counter through the fifth element of the comparison, and the inputs of the processing unit horizon The vertical and vertical elements of the image contour are the inputs of computers of absolute values of the difference of the input signals, the first inputs of which are combined and connected to the output of the first bit of the sequential storage device of the prediction unit, and the second inputs of the third and second bits of the sequential storage device, respectively prediction unit, the first information output of the horizontal and vertical image contour processing unit is the output of the second the comparison element, the second information output - the output of the first comparison element, the third information output - the output of the second register, the fourth information output - the output of the first register, the first control output - the output of the AND element, and the second control output - the output of the OR element.
    3, The device according to claim 1, wherein the unit for evaluating the angular position of the image contour consists of three delay lines, two registers, three accumulators, three comparison elements, AND and OR elements, a weight coefficient calculator and a selector, with
    this first delay line, the OR element, the AND element, the first accumulator, the first comparison element and the first register are connected in series, the second delay line, and the second register, the information input of which is combined with the second input of the AND element, are connected in sequence, the third delay line, the weighting factor calculator and the selector are connected in series, the second accumulator, the second comparison element, the third accumulator and the third comparison element are connected in series between the element output and the second selector input and the input of the first delay line and the second input of the OR element are combined and are the first information input of the image contour position estimation unit, the input of the third delay line, the second input of the weighting factor calculator and the third selector input are combined and are the second information input of the angle position estimation block the image contours, the second inputs of the third delay line and the second accumulator are the third information input, the second input of the AND element is the fourth information input, input sat a wasp entrance is a second delay line control input of - a control input of the first register, the first output - the output of the second register, the second output - the output of the first register, and the third output - the selector output, I
    4, The device according to claim 1, wherein the coordinate discriminator consists of three code converters, a threshold element, a logical unit, a logical-arithmetic unit, a selector, a comparison unit, AND, OR, and EXCLUSIVE OR elements, while the outputs the first two code converters are connected to the inputs of the threshold element, the output of which is connected to the first input of the AND element, the other input of which is connected to the output of the comparison unit, and the output to the first input of the OR element, the second input of the OR element. The first unit is connected to the first input of the logical-arithmetic unit and the first input is connected to the output of the EXCLUSIVE OR element, the output of the OR element is connected to the control input of the selector, the first input of which is connected to the output of the logical-arithmetic unit, and the second input to third converter output
    the code whose inputs are combined with the second, third and fourth inputs of the logical-arithmetic unit, the first inputs of the EXCLUSIVE OR element and the third code converter are the first input of the coordinate discriminator, the third input of the OR element is the second input, the first input of the code converter, the input of the comparison unit The other inputs of the logical-arithmetic unit, the input of the logic unit and the second input of the EXCLUSIVE OR element are the third input of the coordinate discriminator, the inputs of the second code converter are data inputs, and the output selector output coordinate discriminator.
    5. A device according to claim 1, characterized in that the memory block consists of four drives, three memory elements, two keys, a switch and two AND elements, at. In this case, the output of the first accumulator is connected to the first inputs of the two first memory elements, and the input is combined with the inputs of the second storage device and the third memory element, the first output of the second storage device is connected to the second input of the first memory element, the second output of the second storage device is connected to the second input of the second element memory, the output of the third memory element is connected to the inputs of the first element And the fourth storage device, the first input of the first key is connected to the output of the first element And, the second input - with the output of the second element And, the first output one with the third. the input of the second memory element, and the second output - with the third input of the first memory element, the first input of the second key is connected to the output of the third storage device, the second input is connected to the output of the fourth storage device, the input of which is combined with the input of the second element And, the first output of the second key is connected with the fourth input of the second memory element, the output of which is connected to the first input of the switch, and the second output of the second key - with the fourth input of the first memory element, the output of which is connected to the second input of the switch, and the input of the first This drive is the first control to the input of the memory block, the input of the fourth drive is the second control input of the memory block, the fifth inputs of the first and second memory elements are the information input of the memory block, the first and second outputs of the switch are respectively the first and second information outputs of the memory block,
    6, The apparatus of claim 1, wherein the prediction evaluation unit consists of two delay lines, two code converters, two memory elements, four switches, a pulse counter, a comparison element, a trigger, a multiplier, two adders, a selector two elements And and an inverter, while the first input of the first element And through the inverter is connected to the output of the first delay line, the output of which is also connected to the first input of the trigger, the second input of the first element And with the output of the second delay line, and the output with the second trigger input and the output of which is connected via the second .I element I to the input of the first switch, the first input of the multiplier is connected to the first output of the first code converter, and the output to the first input of the second code converter, the second input of which is connected to the output of the reference element, and the output to the input of the second the switch, the second output of the first code converter is connected to the inputs of the comparison element and the first adder, the other input of which is combined with the input of the second adder and connected to the output of the pulse counter, the counting input of which is soy dinene with bus - synchronization, the first input of the third switch is connected to the output of the first adder, the second input is connected to the output of the first adder, the first output is connected to the first input of the first memory element, the second input of which is connected to the first output of the second switch, the third input - to the first output the first switch, the fourth input to the first output of the fourth switch, the fifth input is combined with the first input
     The second memory element and is connected to the output of the second adder, and the output is to the first input of the selector, the second output of the third switch is connected to the second input
    i of the second memory element
    The input is connected to the second output of the second switch, the fourth input to the second, the output of the first switch, the fifth input to the second output of the fourth switch, and the output to the second input of the selector, and the input of the first delay line is the first information input of the evaluation unit forecast inputs
    . the first code converter - the second information input, the second
    and the third multiplier inputs are the third and fourth information inputs, respectively, the second delay line input is the control input, and the selector output is the output of the prediction evaluation unit.
    one
    This invention relates to digital transmission of a television signal and may find application in coding television signals.
    A device for estimating an image contour is known, comprising a serially connected subtraction unit, a quantization and coding unit, and a transmitting unit, the output of the quantizing and encoding unit being connected through the series-connected quantizing and de-encoding unit, adder and prediction unit to another input of the subtracting unit, and the output The prediction unit is also connected to another input of the adder ij.
    However, this device does not achieve good image quality.
    It is also known a device for estimating a contour of an image, comprising a series-connected receiving unit, a quantization and coding unit, an adder and a prediction unit, the output of which is connected to another input of the adder 2,
    However, the known device also does not provide sufficient image quality. The aim of the invention is to improve the image quality.
    The goal is achieved by the fact that, in an image contour estimation device comprising a serially connected receiving unit, a quantization and coding unit, an adder and a prediction unit, the output of which is connected to another input of the adder, the prediction unit consists of a sequential storage device, a horizontal and vertical element processing unit image contour, block of evaluation of the angular position of the contour of the image, coordinate discriminator, three memory blocks, block of prediction estimation, detector signal and selector, while the inputs of the processing unit of the horizontal and vertical elements of the image contour are connected to the outputs of the bits of the serial storage device, the first information output is connected to the first information input of the forecast evaluation unit, the second information output and two control outputs, respectively, to the first information output the input, the reset input and the control input of the evaluation unit of the angular position of the image contour, the third and fourth information outputs to the information inputs are coordinate discriminator, the other inputs of which are connected to the corresponding outputs of the block for estimating the angular position of the image contour, and the output to the information input of the first memory block, the first output of which is connected to the second information input of the forecast estimator, the first control output of the horizontal and the vertical elements of the image contour are connected to the control inputs of the first and second memory blocks, the first information output is connected to the input of the third memory block, the outputs of the three memory blocks With other information inputs of the evaluation unit of the angular position of the image contour, the output of the second memory block — with the second control input of the first memory block, other information outputs of the prediction evaluation block — with additional outputs of the third bit of the consecutive memory of the device, output of the evaluation unit prediction.a - with the selector and detector inputs, the output of which is connected to the selector control input, the other input of which is connected to the output of the first bit of the serial memory the trials. I
    The processing unit of the horizontal and vertical elements of the image contour consists of two calculators of the absolute value of the difference of the input signals, five comparison elements, two summing counters, two registers, elements AND and / / 1I, and an inverter, with the first calculator of the absolute value of the difference. signals, the first element of comparison, the first summing counter and the first register are connected in series, the second calculator is the absolute value of the difference of the input signals. the second comparison element, the second summing counter and the second regis are connected in series, the first input of the OR element is connected to the output of the first meter 1 through a third comparison element, the second input is with the output of the first comparison element through the inverter, the third input is with the output of the second totalizer through the fourth element of the comparison, and the output - by the input of the element I, the second input of which is connected to the output of the second matching counter through the fifth element of the comparison, with the inputs of the horizontal and vertical processing unit The contour elements of the image are the inputs of the calculators of the absolute values of the difference of the input signals, the first inputs of which are connected and connected to the output of the first bit of the sequential locking unit of the prediction unit, and the second inputs of the third and second bits The successors of the sequential storage device of the prediction block, the first information output of the processing block of horizontal and vertical elements of the image contour, is the output of the second element The second information output is the output of the first comparison element, the third information output is the output of the second register, the fourth information output is the output of the first register, the first control output, the output of the AND element, and the second control output is the output of the OR element the angular position of the image contours is soeo of three delay lines / two registers, three accumulators, three elements of comparison, AND and OR elements, a weighting factor calculator and a selector, with the first delay line, the ent OR, the element I, the first accumulator, the first element by comparison, the first register are connected in series, the second delay line and the second register, whose information input is combined with the second input of the AND element, are connected in series, the third delay line, the weighting factor calculator and the selector are connected in series , the second accumulator, the second comparison element, the third accumulator and the third comparison element are connected in series between the output of the element AND and the second input of the selector, with the input of the first line of the selector and the second input of the element OR combine. The yen are the first information input of the image contour angle estimation unit, the input of the third delay line, the second input of the weighting factor calculator, and the third input of the selector are combined and are the second information input of the image angular position estimation block, the second inputs of the third delay line and the second accumulator is the third information input, the second input of the And-che element: the fourth information input, the reset input is the input of the second delay line, the control input - control which is the first input, the first output is the output of the second register, the second output is the output of the first register, and the third output is the output of the selector. Moreover, the coordinate discriminator consists of three code converters, a threshold element, a logic unit, a logical-arithmetic unit, a selector, a unit comparison, elements AND, OR and EXCLUSIVE OR, while the outputs of the two first code converters are connected to the inputs of the threshold element, the output of which is connected to the first input of the element AND, the other input of which is connected to the output the comparison unit and the output to the first input of the OR element, the second input of the OR element is connected to the first output of the logic unit, the second input of which is connected to the first input of the logical-arithmetic unit, and the first input to the output of the EXCLUSIVE OR element, the output of the OR element is connected to control of the selector input, the first input of which is connected to the output of the logical-arithmetic unit, and the second input - to the output of the third code converter, the inputs of which are combined with the second, third and fourth inputs of the logical-arithmetic unit, and the first inputs of the ICSS element) (CEE OR and the third code converter are the first input of the coordinate discriminator, the third input of the I element is its second input, the inputs of the first code converter, the Comparison block input, the other inputs of the logical-arithmetic block, the input of the logic block and the second the input element EXCLUSIVE OR is the third input of the coordinate discriminator, the inputs of the second code converter are information inputs, and the output of the selector is the output of the coordinate discriminator. The memory block consists of four drives, three memory elements, two keys, a switch of the two AND elements, and the output of the first storage device is connected to the first inputs of the first two memory elements. and the input is combined with the inputs of the second accumulator and the third memory element, the first output of the second storage device is connected to the second input of the first memory element, the second output of the second storage device to the second input of the second memory element output of the third memory element - to the inputs of the first element And And the fourth drive, the first input of the first key is connected to the output of the first element I, the second input to the output of the second element I, the first output to the third input of the second memory element, and the second output to the third input of the first memory element first The second input of the key is connected to the output of the third accumulator, the second input is connected to the output of the fourth accumulator, the input of which is combined with the input of the second And element, the first output of the second key is connected to the fourth input of the second memory element, the output of which is connected to the first input of the switch , and the second output of the second key, with the fourth input of the first memory element, whose output is connected to the second input of the switch, the input of the first storage device being the first control input of the memory unit, the input of the fourth storage device the first control input of the memory block, the fifth inputs of the first and second memory elements are informational, the input of the memory block, the first and second outputs of the switch are the first and second information outputs of the memory block, the forecast evaluation block consists of two delay lines, two code converters, two memory elements, four switches, a pulse counter, a comparison element, a trigger, a multiplier, two adders, a selector, two AND elements and an inverter, with the first input of the first And element through an invert p is connected to the output of the first delay line, the output of which is also connected to the first input of the trigger, the second input of the first element I to the output of the second delay line, and the output to the second input of the trigger, the output of which through the second element I is connected to the input of the first switch, the first input the multiplier is connected to the first output of the first code converter, and the output is connected to the first input of the second code converter, the second input of which is connected to the output of the reference element, and the output to the input of the second switch, the second output of the first converter The code recipient is connected to the inputs of the comparison element and the first adder, the other input of which is connected to the input of the second adder and connected to the output of the pulse counter, the counting input of which is connected to the synchronization bus, the first input of the third switch is connected to the output of the first adder, the second input to the output the first adder, the first output - with the first input of the first element of the memory, the second input of which is connected to the first output of the second switch, the third input to the first output of the first switch, the fourth input - to the first output of the fourth switch, the fifth input is combined with the first input of the second memory element and connected to the output of the second adder, and the output to the first input of the selector, the second output of the third switch connected to the second input of the second memory element, the third input of which is connected to the second output of the second switch, the fourth input to the second output of the first switch, the fifth input to the second output of the fourth switch, and the output to the second input of the selector, and the input of the first delay line is the first inf rmatsionnlm input prediction evaluation unit, the inputs of the first code converter informatsionnm second input, second and third inputs of the multiplier - respectively third and fourth data inputs, the second input of the delay line - a control input, and the output of the selector - yield prediction evaluation unit. FIG. 1 is a schematic electrical circuit diagram of an apparatus for evaluating an image contour; FIG. 2 is a structural electrical circuit of the processing unit for horizontal and vertical elements of the image contour; Fig. 3 is a structural electrical circuit of the block for estimating the angular position of the image contour; in fig. 4 is a structural electrical circuit of the coordinate discriminator; Fig. 5 is a structural electrical circuitry of the memory unit; Fig. 6 is a structural electrical diagram of the forecast evaluation unit. The device for estimating the contour of the invention (FIG. 1) comprises a serially connected receiving unit 1, a quantization and coding unit 2, an adder 3 and a prediction unit 4. Prediction unit 4 contains a sequential storage device 5 with bits 6-8, block 9 for processing horizontal and vertical elements of an image contour, block
    10 assess the angular position of the contour of the image 1, the coordinate discriminator 11 and three blocks 12-14 of the memory, block 15 of the forecast evaluation, the detector 16 of the signal and the selector 17.
    Block 9 of processing horizontal and vertical elements of the image contour (Fig. 2) contains two calculators 18 and 19 of the absolute value of the difference of the input signals, five elements 20 - 24 comparisons, two summing counters 25 and 26, two registers 27 and 28, and element 29 , element OR 30 and inverter 31.
    The unit 10 for estimating the angular position of the image contour (Fig. 3) contains three delay lines 32-34, two registers 35 and 36, three accumulators 37-39, three comparison elements 42-42, And 43 element, OR element 44, weight coefficient 45 and the selector 46. The coordinate discriminator 11 (FIG. 4) contains three converters 47 - 49 codes, a threshold element 50, a logic unit 51, a logical-arithmetic unit 52, a selector 53, a comparison unit 54, an AND 55 element, an OR 56 element and an element EXCLUSIVE OR 57.
    Block 12 (13 and 14) of memory (FIG. 5 contains four accumulators 58 - 61, three memory elements 62-64, two keys 65 and 66, a switch 67, and two elements 68 and 69.
    The forecast evaluation unit 13 (Fig. 6) contains two delay lines 70 and 71, two code converters 72 and 73, two memory elements 74 and 75, four switches 76 - 79, a pulse counter 80, a reference element 81, trigger 82, multiplier 83, adders 84 and 85, selector 86, two elements And 87 and 88 and inverter 89.
    The device for estimating the contour of the image works as follows.
    The television signal to be encoded is fed to the receiving unit 1, passes through the quantizing and encoding unit 2, and is fed to the adder 3, which is summed with the prediction value. The output signal of the adder 3 is fed to the prediction unit 4 to the input of the first bit 6 of the sequential memory. Signal x ", x", and and from the outputs. 90-92 bits 6-8, respectively, of the sequential storage device 5 are fed to a block 9 for processing horizontal and vertical elements of the image contour to the inputs of calculators 18 and
    19, where the absolute values of the difference between the signals are calculated respectively | , x |, and
    The signals of the outputs calculate the g ml of the tele 18 and 19 at the inputs of the corresponding comparison elements 20 and 21, on the outputs of which the signal of the logical unit appears, if the absolute values of the differences between the signals 1x-xy1 and 15 (- Xj,., Exceed certain thresholds in reference elements 20 and 21.
    The E signal from output 93 of reference element 20 and the signal EVf)
    5 from the output 94 of the comparison element 21 equal to a logical one indicate the presence of horizontal and vertical elements of the image contour. In the summing counters 25 and 26, the elements of the image contour are counted along each leading edge of the synchronization signal 95 (HP) and the TROUfl signal (output 96)
    5 counters 25 and 26 are reset to zero.
    Thus, the number of 26 elements of the image contour, horizontal from the output of the summing counter 25 and vertical from the output of the summing counter, is counted by the FZCy command, (output 97), is recorded in the registers .27 and 28 (outputs 98 and 99), which give
    information on the number of horizontal tonal fi and vertical on the image contour elements.
    The output signal of the comparison element 24 is equal to one if the output signal of the second cy 1-counting counter 26 is greater than one, indicates the presence of the first vertical element of the image contour and is zero when zeroed by the TROUj signal, which adds up the count of 26. The TROU signal is intended to mark the contour intervals images and shows: it contains or does not contain vertical elements in it, if there are no horizontal elements, the signal from the output of summing counter 26 is zero, and the output of inverter 31 is one, if horizontal elements are present, the contents of which summing meters 25 and 26 exceed six.
    Elements 22 and 23 of the comparison are triggered at a value of 7, the signal
    from the output of the comparison element 22 is equal to one, if from the output 100 of the summing 25 signal, and the signal from the output of the comparison element 23 is also equal
    unit, if the signal V 7 is output from the output 101 of the summing counter 26. At the output 96 of the element OR 30, the signal TROUf is produced ,. Element 29 (output 97) generates an FZCri signal and indicates that the image contour contains at least one vertical element.
    horizontal contour elements
    The signals EH, TROU and FZCj, from the corresponding outputs 93, 96 and 97 of block 9, are fed to block 10 of the estimation of the angular position of the contour of the image.
    The TROUf signal arrives at the input of the delay line 33, from output 102 the delayed signal TROUn-i is fed to the input of register 36, the signal S from output 103 of which contains information about the orientation of the image contour.
    The delay line 32 is triggered by the synchronization signal 95, and the E signal is sent to its input, from One of the outputs 93 of block 9, which also goes to one of the inputs of the OR 44 element, to the second input of the OR element 44, the E signal delayed by the delay line 32 is applied, and the signal from the output of the element OR 44 is fed to the input of the element AND 43 whose second input is combined with the input of the register 36 and to which the signal EV | is output from the output 104 of the memory block 14.
    The control of the signals TROUf) and FZC Y requires an appropriate adjustment of the delay of the synchronization signal 95. Registers 27 and 28 must be reset to zero before summing counters 25 and 26.
    In tab. 1 shows the variation of various signals.
    Table 1
    vertical contour elements
    From the output 105 of the element I 43, the signal EVZf enters two processing channels, the first of which contains a drive 37, an EVC signal, from the output 106 of which through the reference element 40 (output 107) and the signal T1 arrive at the input of the register 35. The TG signal from the output 108 of register 35 indicates the presence of vertical image contour elements located directly above the image being processed, including cheers,
    The second processing channel contains accumulator 38, the reset input of which receives the signal FZCjj from the output 109 of memory 13 and the signal AEVZ from output 110 to the input of the comparison element 41, one from the 111 input of the comparison element 41, the DEVZ signal) accumulator 39, the FCH signal from the output 112 of which, via element 42, compares with the unit: the control signal PREM for the selector 46 (output 113).
    The operation of the two processing channels is shown in Table. 2 and 3.
    Table 3
    In the same block 10, the input E of the delay line 34, controlled by the FZCi signal, receives the signal E from the output 114 of the memory block 12, from the output 11S of the delay line 34, the signal E {goes to the weighting factor calculator 45, to which the undelayed signal E arrives. and from output 116 - c signal.
    Thus, the signal A, EVZ from the output 1LO of the accumulator 38 takes into account the vertical elements of the image contour related to the previous line, the signal DEVZn from the output 111 of the comparison element 41 contains information about the detection of initial instants when the AEVZ signal is non-zero and arrives accumulate 39. Comparison element 42 generates a control signal if the FCHfl signal from output 113 of accumulator 3 is not zero (Table 3). The output 117 of the selector 46 is the third output of block 10, this signal E g is divided into five components: H, V, NM, Q and S (outputs 118-122). In order to simplify the separation into components in FIG. 3 not shown.
    The inputs of the first converter 47 of the code receive the signals H and V, the inputs of the second converter 48 of the code receive the signals H and V from the outputs 98 and 99 of the registers 27 and 28 of block 9. The signals 8 and b from the outputs 123 and 124 of the converters 47 and 48 of the codes arrive at the inputs of the threshold element 50. These signals biv give information about the absolute value of the former and observed angles. In tab. Figures 4 and 5 show two options for converting the angle S depending on the average number of horizontal H and vertical V elements of the image contour.
    Table 4
    Continued table. 4 2
    0.4 s Z i 0.9
    0.2 Z 60.4
    Z i 0,2
    Table 5
    .. H-V + 1 si H V
    0 V-H + I si H cV
    t 3,4
    2.1 -: t 3.4
    1,4 t 6 2, 1
    HX V
    1 it 6l, 4
    1 Jtt il, 7
    1.7. t6 3
    H.V
    3 .i t 68
    The threshold element 50 calculates the absolute difference of the signals S and 9, greater than or equal to l b, where db -. threshold value to set. Comparison unit 54 Comparing the signal NM d with a twain, the output signal of unit 54 is one if the signal NM is greater than or equal to two. The RUPTQ signal from element 125 output 125 indicates a discontinuity in the absolute value of 9 only if the length of the observed image contour is sufficient.
    Signals S and 5 are received at the inputs of the EXCLUSIVE OR 57 element.
    from output 126, the SS signal together with the Q signal is processed in logic block 51, the logic of which is presented in Table. 6 and 7. The signal b from the output 127 of the logic block 51 indicates a sign break, for at least two successive lines. The RUPTS signal is removed from the output 128 of the logic unit 51.
    Table
    Table
    In tab. 9 shows the digitization of the components of the used signals E, EJ,
    Element OR 56 combines the signals TI, RUPTQ and RUPTS. The resultant signal is a control for the selector 53 and selects two EE 5 or El signals to its inputs. Logical and arithmetic unit 52, the inputs of which sig; H, V, S, H, V, NM, Q, NS, NP, and the signal NS (input 129) reflects the number of vertical elements of the image contour that are not related to the number of horizontal elements of the image observed in the lines preceding line, and the second signal NP (input 130) reflects the sum of the observed characters during the contour tracking. The logic of the logical-arithmetic unit 52, with output 131
    0 of which the signal EE is taken, the logic of operation of the converter 49 of the code, from the output 132 of which is removed: the signal Et, is presented in tab. 8 .. In addition, from the output of 133 selectors
    5f, signal E is taken.
    Table
    E; Е ,, В, Е, ЕЕ, EI, fe tabl. 10, the correspondence between the components E, E, and c. . Note:
    Table In all cases, this number takes all the rational values of the segment .0,8lj resolved by imegadims b.e. for example for 4 b.e. the discretization step, therefore, will be equal to 0.5, and the allowed values will be O-, 0.5; IV l, 5j 2; 2.5; 3; 3.5; four; 4.5; five; 5.5; b, 6.5, 7, 7.5; INSI prints the sign 5, denoted NS (NSJ, NS, NS /, NSB, NS, NSE, NSI) and is used with this designation in Table. 5 and 9, Table 10; Е Е, В II If NM NM, (#I, MM.) 5. I, II n H, YV locS H + (1- (X) s, I, I vv | VB ct V + Ll-ot), II NP NP NPB ctNP-t- (1-L) NP 20 I NS NS | NSB odNS + (1-rt) Ns,, QQ QB О Signal E from the output 133 of the selector 46. coordinate discriminator -, "11 enters into the memory block 12 to the inputs of two elements 62 and 63 of the memory, the signal FZCri from the output 97 of the element I 29 of block 9 is fed to the input of the third memory element 64 and the inputs of two drives 58 and 59. Here, the elements 62-64 of memory and drive 58 are triggered by a synchronization signal 95. The drive 58 is reset to zero by the start line DL signal (input 134), the AE signal from output 40 135 of which goes to the second
    2nd drive
    1st key 65 59
     OL,
    OE,
    OE,
    Pl o
    Fzc
    OL
    Fzc
    ABOUT
    OLJ
    The recording signal is an AE signal from output 135 of accumulator 58, which is reset to zero by the DL signal. The read instructions for the preceding line are received at the output of the AND 68 element. The read commands are switched in the key 65 by the action of the parity command PL. lines (tab. 11). Getting read addresses related to previous 10 25
    2nd key 66
    switch 67
    E
    AL,
    Ej
    AL.
    AL
    OLJ
    Alj
    AL
    Alj
    the line that proceeds to the current line with a delay is achieved according to the same principle. The reset command is a DL signal, the switch is performed in the key 66 under the effect of the signal PL (table 11). The same signal PL controls the switch 60,
    Work blocks 13 and 14
    similar to the operation of memory block 12. inputs of memory elements 62 and 63; In addition, drive 59 has a parity line signal PL (input 136), OE and OE signals from outputs 137 and ® of which are fed to the third inputs of memory elements 62 and 63. Signal Rgs „. | from the output 139 of the memory element 64, is applied to the first inputs of the element I 68 and the accumulator 60 controlled by the DL signal. The output element And 68 is connected to one of the inputs of the first key 65, and the output of the third accumulator 60 is connected to one of the inputs of the second key 66. The FZCn signal is fed to the first inputs of the And 69 element and the accumulator 61, controlled by the HP signal and reset to zero by the DL signal . The output of the element 69 is connected to another input of the first key 65, and the output of the accumulator 61 to the other input of the second key 66. The signals OL and OLj from the outputs 140 and 141 of the first key 65 are fed to the corresponding inputs of the memory elements 62 and 63, the signals AL , and Lj from the outputs 142 and 143 of the second key 66 are also fed to the corresponding inputs of the memory elements 62 and 63. The shields e, and gj from outputs 144 and 145. memory elements 62 and 63 are fed to the inputs of switch 67, from which outputs 114 and 146 of which signals E and EJ are respectively removed. The first memory element 62 informs about the current line, and the second memory element 63 about the previous line, while switching at each line change takes place in accumulator 59, keys 65 and 66, switch 60 with control signal PL (O or 1) , indicating the parity of the line according to the table, 11. Table 11
    the FZCn signal from the output 109 of the memory block 13 is fed to the input of the block 10. The EV signal from the output 104 of the memory block 14 is also fed to the input of the block 10. The input of the memory block 12 is fed to the FZC signal from the output 97 of the block 9, and input - memory block 14 - signal EV from output 94 of block 9.
    In memory block 12, the signal EJ from output 146 has two components HJ and VJ, which are fed to inputs 147 and 148 of converter 72 of the code of prediction evaluation block 15. The same block 15 receives signals x „., And x„, (from outputs 149 and 150 of the third bit 8 of the sequential storage device 5 to the inputs of the multiplier 83), the signal from the output of block 9 to the input of the delay line 71, and EV signal from block 9 output to line input
    70 delays. The EV signal is stored in the delay line 70 triggered by the HP signal for J periods of the HP synchronization signal; FZCj is memorized in line
    71 delays triggered by the HP signal for the J + 1 period of the HP signal. The leading edge of the delayed signal delay line 70 transfers the trigger 82 to the state one and is inverted by the inverter 89. The output signal of the AND element 87 is the result of the logical operation AND inverted signal - and the signal FZCj. The output of the element And 87 brings the trigger 82 to the zero state. The trigger output 82 indicates
    that the point is between the first vertical element of the image contour and the end of the image contour, including the edges,
    In tab. 1-2 illustrates the switching of various signals necessary for the operation of memory elements 74 and 75.
    Table
    Continued table. 12
    1/2
    1/2
    1/4 6
    1/2
    At the command of the OE signals from the output. 151 elements And 88 is carried out. Recording of the signal PPP-3 - output 152 of the converter 73 code to the address of the signal AEP from the output 153 of the adder 85.
    Suppose that the signal PL 1, in this case, for the memory element 70 from the output 154 of the switch 76 is an OEPP signal, OE, and from the output 155 of the switch 77 is the signal .j, the write address is from the output 156 of the switch 78 a signal that, due to the summator logic 85 is equal to Hvj + 2 NDECAJ, where NDECAJ is the signal from the output 157 of the converter 72 codes, n is the index of the point counted in the pulse counter 80, which is reset to zero at the beginning of the line, and the signal NDECAJ is a function of the estimated angle of the observed contour at the point and - J.
    The NDECAJ signal is obtained by converting the HJ and VJ signals to the inputs 147 and 148 of the code, according to
    63, the resulting table is obtained. 12. Angle 4 and 5. According to Table.
    With the signal PL 1, the memory element 75 operates in such a way that with each HP synchronization signal (signal OLPP2 HP from the output 158 of the switch 79), reading from the memory element 75 is performed using the + 1 signal from the output 159 of the adder 84, the selector. 86 gives the result
    this readout (signal .P-, where signal P is removed from output 160 of selector 86, and signal PP from output 161 of switch 77). After a read is performed, the memory element 75 at the same address is reset to zero (the AEPP signal of the ALPP, where the signal is taken from the output 162 of the switch 7§), the value of zero is written to the memory element 75 (the signal ). 5 Sync signal recording
    OEPP2 from output 163 of switch 76 is an HP synchronization signal supplied with a delay to the input of switch 76, and the delay is determined by a read cycle at which the RHZ signal is generated. Thus, in memory elements 75 and 74, during the duration of the synchronization period H-P. First must be read and then write.
    With PL O, the memory blocks work inversely with respect to the case when PL 1. In the same block 15, multiplier 83 produces at its output 164 a signal VPP.j
    (1 - p) -x ".- i + yJ-xp-zm" where the signal yj is taken from the output 165 of the converter 72 of the code.
    Signal values of 3, obtained in the converter 72 code, are listed in Table. 12,
    .
    Next, the NDECAJ signal is given
    Comparison element 81, the DECA 1 signal is output from 166, EZ signal P, output 160 of block 15 is fed to signal detector 16, the COM signal from whose output together with the signal goes to inputs of selector 17, to the third of which the signal Hu arrives. The signal detector 16 detects a zero value if the signal, then the signal COM at the output 168 detects the signal 16 signal equal to one, and the output P9, + - passes to the output 169 of the selector 17. If the signal PH + is a COM 0 signal and a comparison selection 81, if the signal is NDECAJ 7, in other cases the signal is TDECA 0. The code converter 73 converts the PP-3 signal according to Table 13. Table 13
    ten
    15
    20
    The operation of the switches 76 - 79 and selector 86 is presented in table. 14, where the OLPP signal is removed from the output 167 of the switch 79.
    , Table14
     PV,
    torus 17 issues a signal
    FOR
    + 1
    nt1 prediction,
    Thus, the present invention allows to improve the quality of the image, which is formed predominantly by lines consisting of equidistant points located in the centers of the rectangles formed by a double beam of lines intersecting at a right angle,
    0 as well as when all the lines contain a certain number of points forming the video signal line, and the number of points depends on the accepted standard.
    1
    FIG.
    .
    95 I
    权利要求:
    Claims (6)
    [1]
    1. DEVICE FOR EVALUATING AN IMAGE CIRCUIT, containing a series-connected receiving unit, a quantization and coding unit, an adder and a prediction unit, the output of which is connected to another input of the adder, characterized in that, in order to improve the image quality, the prediction unit consists of sequential memory device, processing unit of horizontal and vertical elements of the image contour, unit for evaluating the angular position of the image contour, coordinate discriminator, three memory blocks, bl an eye for forecast estimation, a signal detector and a selector, while the inputs of the processing unit of horizontal and vertical contour elements!
    the images are connected to the outputs of the bits of the serial storage device, the first information output is to the first information input of the forecast estimation unit, the second information and two control outputs are, respectively, to the first information input, the Reset input and the control input of the image contour angular position estimation unit, the third and even the fourth information outputs - to the information inputs of the coordinate discriminator, the other inputs of which are connected to the corresponding outputs of the angular estimation unit the position of the image contour, and the output, by the information · input of the first memory block, the first output of which is connected to the second information input of the forecast estimation block, while the first control output of the processing unit of horizontal and vertical elements of the image contour is connected to the control inputs of the first and second memory blocks , the first information output - with the input of the third memory block, the outputs of the three memory blocks - with other information inputs of the block for estimating the angular position of the image contour, the second output a storage unit - to the second control input of the first memory block, the other data inputs of block progyo- evaluation. for - with additional outputs; rub. its discharge sequential storage device, the output of the block '>
    forecast estimates — with the inputs of the selector and detector of the signal, the output of which is connected to the control input of the selector, the other input of which is connected to the output of the first discharge of the sequential storage device.
    [2]
    2. The device according to claim 1, characterized in that the processing unit of horizontal and vertical elements of the image circuit consists of two calculators of the absolute value of the difference of the input signals, five comparison elements, two summing counters, two registers, elements
    And both OR and the inverter, while the first calculator of the absolute value of the difference of the input signals, the first comparison element, the first summing counter and the first register are connected in series, the second calculator of the absolute value of the difference of the input signals, the second comparison element, the second summing counter and the second register are connected in series, the first input of the OR element is connected to the output of the first totalizing counter through the third comparison element, the second input is connected to the output of the first comparison element through the inverter, the third input od - with the output of the second totalizing counter through the fourth comparison element, and the output - with the first input of the element And, the second input of which is connected to the output of the second totalizing counter through the fifth comparison element, the inputs of the processing unit for horizontal and vertical image contour elements are . of absolute values of the difference of input signals, the first inputs of which are combined and connected to the output of the first discharge of the sequential storage device of the prediction unit, and the second inputs respectively, to the outputs of the third and second bits of the sequential memory of the prediction unit, the first information output of the processing unit of horizontal and vertical image contour elements is the output of the second comparison element, the second information output is the output of the first comparison element, the third information output is the output of the second register, and the fourth information output - the output of the first register, the first control output is the output of the AND element, and the second control output is the output of the ele cop OR.
    [3]
    3. The device according to claim 1, wherein the evaluation unit for the angular position of the image contour consists of three delay lines, two registers, three drives, three comparison elements, AND OR elements, a weight calculator and a selector, with this is the first delay line, the OR element, the AND element, the first drive, the first comparison element and the first register are connected in series, the second delay line, and the second register, the information input of which is combined with the second input of the AND element, are connected in series, the third line delays, a weight calculator and a selector are connected in series, the second drive, the second comparison element, the third drive and the third comparison element are connected in series between the output of the AND element and the second input of the selector, and the input of the first delay line and the second input of the OR element are combined and are the first information input of the block for estimating the angular position of the image contour, the input of the third delay line, the second input of the weight calculator and the third input of the selector 'are combined and are the second information input of the block for estimating the angular position of the image contour, the second inputs of the third delay line and the second drive are the third information input, the second input of the element, And is the fourth information input, the reset input is the input of the second delay line, the control input is the control input of the first register , the first output is the output of the second register, the second output is the output of the first register, and the third output is the output of the selector.
    ί '
    [4]
    4, The device according to claim 1, characterized in that the coordinate discriminator consists of three code converters, a threshold element, a logical unit, a logic-arithmetic unit, a selector, a comparison unit, AND, OR, and EXCLUSIVE OR elements, while the outputs of the first two code converters are connected to the inputs of the threshold element, the output of which is connected to the first input of the AND element, the other input of which is connected to the output of the comparison unit, and the output to the first input of the OR element, the second input of the OR element is connected to the first output logically of the second block, the second input of which is connected to the first input of the logic and arithmetic block, and the first input to the output of the EXCLUSIVE OR element, the output of the OR element is connected to the control input of the selector, the first input of which is connected to the output of the logic and arithmetic block, and the second input to the output the third code converter, the inputs of which are combined with the second, third and fourth inputs of the logic-arithmetic block, with the first inputs of the element ISKLYU-. The singing OR and the third code converter are the first input of the coordinate discriminator, the third input of the OR element is its second input, input1 of the first code converter, input of the comparison unit, other inputs of the logic-arithmetic block, the input of the logical block and the second input of the EXCLUSIVE OR element are the third input of the coordinate discriminator , the inputs of the second code converter are information inputs, and the selector output is the output of the coordinate discriminator.
    [5]
    5. The device pop. 1, characterized in that the memory unit consists of four drives, three memory elements, two keys, a switch and two elements And, with. the output of the first drive is connected to the first inputs of the first two memory elements, and the input is combined with the inputs of the second drive and the third memory element, the first output of the second drive is connected to the second input of the first memory element, the second output of the second drive is connected to the second input of the second memory element, the output of the third memory element is connected to the inputs of the first element And and the fourth drive, the first input of the first key is connected to the output of the first element And, the second input is the output of the second element And, the first output third. the input of the second memory element, and the second output with the third input of the first memory element, the first input of the second key is connected to the output of the third drive, the second input is the output of the fourth drive, the input of which is combined with the input of the second element And, the first output of the second key is connected to the fourth the input of the second memory element, the output of which is connected to the first input of the switch, and the second output of the second key is the fourth input of the first memory element, the output of which is connected to the second input of the switch, the input of the first The drive is the first control input of the memory unit, the input of the fourth drive is the second control input of the memory unit, the fifth inputs of the first and second memory elements are the information input of the memory unit, the first and second outputs of the switch are the first and second information outputs of the memory unit, respectively.
    [6]
    6. The device according to π. 1, characterized in that the forecast estimation unit consists of two delay lines, two code converters, two memory elements, four switches, a pulse counter, a comparison element, a trigger, a multiplier, two adders, a selector, two AND elements and an inverter, the first the input of the first And element through an inverter is connected to the output of the first delay line, the output of which is also connected to the first input of the trigger, the second. the input of the first element And with the output of the second delay line ·, and the output is with the second input of the trigger, the output of which is through the second element And is connected to the input of the first switch, the first input of the multiplier is connected to the first output of the first code converter, and the output to the first input of the second code converter, the second input of which is connected to the output of the comparison element, and the output to the input of the second switch, the second output the first code converter is connected to the inputs of the comparison element and the first adder f another input of which is combined with the input of the second adder and connected to the output of the pulse counter, the counting input of which is connected to the synchronization bus nation, the first input of the third switch is connected to the output of the first adder, the second input to the output of the first adder, the first output to the first input of the first memory element, the second input of which is connected to the first output of the second switch, the third input to the first output of the first switch, fourth input - to the first output of the fourth switch, the fifth input is combined with the first input ί of the second memory element and connected to the output of the second adder, and the output to the first input of the selector, the second output of the third switch is connected n with the second input i of the second memory element, the third input of which is connected to the second output of the second switch, the fourth input to the second output of the first switch, the fifth input to the second output of the fourth switch, and the output to the second input of the selector, and the input of the first line Delay is the first information input of the forecast estimation block, inputs. the first code converter with the second information input, the second and third inputs of the multiplier — the corresponding delay line — controlling the third and fourth inputs respectively, and the selector output — the output with information inputs, the input of the forecast estimation second block.
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    同族专利:
    公开号 | 公开日
    JPS56500830A|1981-06-18|
    US4363103A|1982-12-07|
    ES8103531A1|1981-02-16|
    DE3066373D1|1984-03-08|
    EP0021948A1|1981-01-07|
    FR2460580A1|1981-01-23|
    WO1981000180A1|1981-01-22|
    EP0021948B1|1984-02-01|
    ES492865A0|1981-02-16|
    CA1163359A|1984-03-06|
    FR2460580B1|1984-03-23|
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    法律状态:
    优先权:
    申请号 | 申请日 | 专利标题
    FR7916914A|FR2460580B1|1979-06-29|1979-06-29|
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